Nitheesh Appala

Nitheesh Appala is currently an ASIC Hardware Design Engineer at Abacus Semiconductor Corporation since September 2023, focusing on the RTL upgradation of DDR3 memory controllers to support DDR5 and LPDDR5 configurations, and optimizing code for PPA requirements. Prior experience includes serving as a Physical Design Intern at Intel Corporation from July 2022 to June 2023, where Nitheesh engaged in the construction flow of HDK and Cheetah environments in Synopsys Fusion Compiler, and worked on post silicon validation methodologies and debugging. Nitheesh began the career as a Data Analyst at Infosys from April 2020 to May 2021. Educational qualifications include a Master of Science in Electrical and Computer Engineering from Portland State University, currently ongoing, and a Bachelor of Technology in Electrical, Electronics and Communications Engineering from KL University.