Peter Tufvesson

Peter Tufvesson is an experienced FPGA and ASIC designer with extensive expertise in system architecture and integration within the semiconductor industry. Currently serving as an FPGA designer contractor at Advenica AB since August 2020, Tufvesson has previously held significant roles such as ASIC System Architect at Ericsson, where involvement included high-level SoC projects in advanced technology nodes (7nm/5nm). Additional experience encompasses ASIC design and development at Acconeer AB, as well as system engineering for the first commercial LTE handset chip at Ericsson Mobile Platforms. Tufvesson's career showcases a strong foundation in digital ASIC design, power optimization, and system management, supported by a Master of Science in Computer Science from Lund Tekniska Högskola.