Arteris
Cheryl Lin, CPA, CA has a strong background in accounting and finance, spanning over a decade of experience. Cheryl currently holds the position of Assistant Corporate Controller at Arteris IP since August 2022. Prior to this, they worked at Arteris IP as the Senior Director of SEC Reporting and Technical Accounting from October 2021 to August 2022, and as the Director of SEC Reporting and Technical Accounting from May 2021 to October 2021.
Before joining Arteris IP, Cheryl was employed by Okta as the Senior Manager of Technical Accounting & Reporting from May 2020 to April 2021. Cheryl'sprevious role at SunPower Corporation was as the Technical Accounting Manager from November 2015 to May 2020.
Cheryl began their professional career at PwC, where they worked as a Senior Audit Associate from December 2013 to November 2015. Prior to that, they worked at KPMG as a Senior Audit Associate from July 2011 to December 2013. At KPMG, Cheryl gained experience in financial statement auditing, internal staffing of engagements, project scheduling and budgeting, and audit advisory services.
Cheryl's career in finance started with an internship at UPEK from December 2007 to April 2008. Cheryl has also obtained the Chartered Accountant of Singapore (CA (Singapore)) designation.
Overall, Cheryl Lin's work experience demonstrates their expertise in technical accounting, SEC reporting, audit, and financial analysis across various industries.
Cheryl Lin, CPA, CA, has a diverse education history that includes a Bachelor of Accountancy (B.Acc) degree from Nanyang Technological University Singapore, specializing in Accountancy with a second specialization in Information Technology.
Cheryl also participated in an International Student Exchange Program at Bentley University in the fall of 2010.
In 2011, they joined the Global Immersion Program at SYMBIOSIS INTERNATIONAL UNIVERSITY. Prior to their university education, Cheryl attended Saint Andrew's Junior College where they obtained their GCE 'A' Level certification.
In addition to their formal education, Cheryl has also acquired several certifications. Cheryl is a Registered Yoga Teacher with a 200-hour certification from Yoga Alliance, obtained in December 2017. Cheryl is also a Certified Public Accountant (CPA) registered with the California Board of Accountancy, which they obtained in November 2015. Furthermore, Cheryl holds the Chartered Accountant of Singapore designation from the Institute of Singapore Chartered Accountants (ISCA), obtained in November 2014.
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Arteris
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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.