Arteris
Sonia (Xiao-ou) Zhang has diverse work experience in finance and business operations. Sonia (Xiao-ou) is currently working as the Director of FP&A at Arteris IP since July 2021. Prior to that, they were the Senior Manager of Finance and Business Operations at Upwave from October 2019 to June 2021. Sonia also served as the Senior Finance Manager at Hustle from October 2018 to September 2019. Before that, they worked as the Senior Manager of Finance at BrightEdge from December 2014 to October 2018. Sonia (Xiao-ou) also worked as a Senior Reporting and Analytics Analyst at HGST, a Western Digital company, from January 2014 to November 2014. Earlier in their career, Sonia worked as an Accountant/FP&A at BoardVantage from February 2012 to October 2013, and as an Accounting Intern at BoardVantage, Inc from July 2011 to October 2011. Sonia (Xiao-ou) began their professional journey as a Research Assistant at the Leavey School of Business from October 2010 to June 2011.
Sonia (Xiao-ou) Zhang completed their Bachelor of Management degree in Management Information System at Beijing University of Posts and Telecommunications in 2007. After that, they pursued their MBA at Santa Clara University Leavey School of Business specializing in Accounting and Finance from 2009 to 2012.
Arteris
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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.