Leonid Bell

Leonid Bell is a seasoned professional in the field of VLSI design and verification, currently serving as a Senior Logic Design Engineer at CEVA, Inc. since October 2022, where responsibilities include RTL design of DSP modules and test verification. Previous experience includes roles as an Emulation Engineer at Qualcomm, where prototyping of ASIC RTL on FPGA systems was a key focus, and as an FPGA R&D professional at SCD, overseeing the development of FPGA-based systems. Leonid has also held managerial positions at Intel Corporation, leading a team in system validation of network processors, and at Freescale as a SoC Architect. Additional expertise was gained at Broadcom in developing video processing IPs and at Mindspeed Technologies in the verification of telecommunication ASICs. Leonid's academic background includes a Master's degree in VLSI architectures from Technion and a Bachelor's degree in Electrical systems from National Technical University "Kharkiv Polytechnic Institute."