Deepal Shrishrimal

Deepal Shrishrimal is a highly skilled Sr Staff Digital Design Engineer at Cirrus Logic, with extensive experience in digital ASIC design, specializing in mixed signal designs, A/D interfaces, and custom multiply-add blocks for application-specific operations. Deepal's professional journey began with a Bachelor of Engineering from Sinhgad College of Engineering, followed by a Master's degree in Electrical and Electronics Engineering from North Carolina State University, where a GPA of 3.8 was achieved. Additional experience includes an internship as a Digital Design Engineer at Cirrus Logic, focusing on DSP core verification, and a prior role as a Software Engineer at Infosys Technologies Ltd.