Dr.-Ing. Zheng Gu

Zheng Gu, Dr.-Ing., is a seasoned expert in analog and mixed-signal design with extensive experience in leading engineering teams across reputable companies. Currently serving as a Senior Team Lead at Cyient since April 2020, Zheng Gu previously held roles at Intel Corporation as a Senior Staff Engineer, where responsibilities included leading RF and mixed-signal design efforts, supervision of circuit design teams, and development of critical RF components for cellular transceivers. Prior to Intel, engagements included leadership positions at Lantiq in RF & mixed-signal design and project management, as well as contributions to advanced DRAM technology at Qimonda and Infineon Technologies. Educational credentials include a Dr.-Ing. degree from Paderborn University and a Master's degree from Southeast University. Achievements encompass the development of high-volume products in cutting-edge CMOS technologies and significant contributions to various memory and communication technologies.