Jay Schleicher

Since 1990, Jay has been involved in nearly every aspect of FPGA software development, such as new architecture development and support, research, synthesis, IP development, Q/A, verification, and simulation. At Efinix, his goal is to build a complete, best-in-class RTL-to-bitstream FPGA CAD flow.

Previously, Jay spent 23 years at Altera leading software and IP teams in a variety of areas. For example, he led the team that developed an in-house synthesis tool that is considered a best-in-class tool. Jay also led the software team that analyzed and experimented with new architectural features, and assessed, from a software perspective, whether a feature would be desirable or undesirable.

Jay has extensive experience reviewing, analyzing, and evaluating patentable ideas, and he has authored or co-authored more than 50 patents.