Habeeb Farah

Habeeb Farah has extensive work experience in the technology industry. Habeeb started their career at Intel Corporation in 1997 as a Software Engineer, where they developed logic synthesis tools for logic verification. Habeeb then moved on to become the Project Leader of RTL compilers, managing the development of iHdl, Verilog, and VHDL compilers. During this time, they also transitioned into working with V2K and System Verilog. Farah worked at Intel Corporation until 2003.

In 2004, Farah joined Intel Corporation again, this time working in the field of formal analysis technologies for logic power optimization and High-Level Design. Their work involved implementing complex algorithms for automatic clock gating and power saving using formal analysis mechanisms. Habeeb also deployed Formal-based High-Level Design to circuit systems and developed methodologies.

From 2010 to 2013, Farah worked at Jasper Design Automation, where they held the role of R&D Director. Habeeb was responsible for research and development of formal Apps and solutions, specifically focusing on formal coverage and sequential equivalence verification domains. Habeeb also worked on building platform architecture infrastructure.

In 2014, Farah joined Cadence Design Systems as a Software Engineering Director. Habeeb later became the Software Engineering Group Director in 2015.

Throughout their career, Farah has demonstrated expertise in software engineering, microarchitecture performance modeling, formal analysis, and development of CAD tools. Habeeb has also contributed to the advancement of technology through their US-patented work in logic design development.

Habeeb Farah obtained a BSC degree in computer engineering from the Technion - Israel Institute of Technology. Habeeb attended the institute from 1990 to 1993.