Jasper Design Automation
Koen Claessen is a Professor at Chalmers University of Technology and a Senior Researcher at Jasper Design Automation, holding positions since 2004. Prior roles include Senior Researcher at Safelogic AB from 2001 to 2003 and Assistant Professor at Chalmers University of Technology during the same period. Koen Claessen earned a PhD in Computing Science from Chalmers University of Technology between 1998 and 2001, and a drs. in Computing Science from Utrecht University from 1994 to 1997.
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Jasper Design Automation
Upgrade Your Design and Verification with Jasper! Jasper Design Automation's mission is to make full formal IC verification a competitive advantage for its customers. Jasper's formal verification solutions are used by logic designers, verification engineers and silicon bring-up teams to design, explore and debug RTL, to ensure correctness of block-level functionality and for rapid post-silicon validation and debug.