FPGA Digital Design Engineering Intern

Kepler is on an audacious mission: to bring the internet to space. Founded in 2015, our ambition is to provide internet connectivity in space, whether in LEO, MEO, GEO, or beyond. With an expanding base of early customers and our first 23 satellites in orbit, Kepler is continuing to grow and expand its most important asset – the Team!

This position requires candidates to be available for 4-16 months starting May or September 2025.

We invest heavily to deliver the best products to our customers, and so we’re on the hunt for a top-tier FPGA Digital Designer Engineer Intern. The RTL code you write will contribute to our new generation of satellites and earth stations. 

Responsibilities

• Maintain and add new functionality to our FPGA code base, including code to control and test our SDR (software-defined radio) and SDN (software-defined network);
• Design custom IP for new features of both Kepler's satellites and ground stations;
• Add support for new sensors/communication interfaces (such as SPI, I2C, UART);
• Work with high-speed FPGA interfaces (e.g. JESD204b, 10G Ethernet, Aurora).

Requirements

• 2+ years in an Electrical or Computer Engineering degree program, or equivalent;
• Experience with Verilog, SystemVerilog, or VHDL. (You will be working in SystemVerilog).

Bonus Points

• Acceptance into a Masters in Electrical or Computer Engineering, or equivalent;
• Experience with DSP (digital signal processing) algorithms;
• Strong skills with C++ and embedded programming;
• Strong scripting experience (e.g. bash, Python, Tcl, etc.);
• Relevant experience through hobbies or a university design team.