Denis Rheault

Denis Rheault is a seasoned engineer with extensive experience in ASIC and FPGA design, currently serving as a Senior ASIC/FPGA Design Engineer at Marvell Technology since September 2022. Previously, Denis worked as an FPGA Designer at Rockport Networks Inc. and held multiple prominent roles at Nokia, including FPGA Design and Verification Engineer, contributing to the design and verification of OTN FPGAs, G.Fast ASICs, and various hardware design projects. Denis's expertise encompasses VHDL/Verilog/SV RTL coding, UVM verification, and integration of complex protocols, along with significant improvements in design methodologies and cost optimization. Earlier roles included Functional Test Engineer and Technology Development Engineer at Newbridge Networks, further showcasing a comprehensive background in hardware simulation and test methodologies. Academic credentials include a degree from the University of Ottawa and studies at Télécom Paris.