Joung Youn Kim

Joung Youn Kim is a seasoned professional in ASIC design and development with extensive experience in the semiconductor industry. Currently serving as a Senior Staff ASIC Design Engineer and Manager at Marvell since May 2010, Joung Youn Kim focuses on defining bus architecture to optimize system-level performance while managing trade-offs between operating frequency and latency. Prior experience includes a position as a Senior Staff Researcher at DongBu Hitek, where responsibilities encompassed ISP algorithm development and hardware/software design, and as a Member of Technical Staff at MagnaChip Semiconductor, involved in algorithm development and digital logic design for CMOS image sensors. Joung Youn Kim holds both an MS and PhD in Electrical Engineering from the Korea Advanced Institute of Science and Technology and a BS in Electrical Engineering from Yonsei University.