Sijin C Johnson

Sijin C Johnson is a Design and Verification trainee at Maven Silicon, with experience in Digital Design, RTL coding using Verilog, System Verilog for Verification, and Universal Verification Methodology since August 2018. Prior to this role, Sijin completed an internship in the Analog Validation Domain at Silicon & Beyond, working on the project 'Analysis of analog IP's embedded in High Speed SERDES' from August 2017 to August 2018. Educational qualifications include a Master of Technology (MTech) in Microelectronics from Manipal Institute of Technology (2016-2018) and a Bachelor of Technology (BTech) in Electronics and Communications Engineering from Vidya Academy of Science and Technology (2010-2014), as well as earlier studies in Computer Science and foundational subjects.