Liang Zhou

Liang Zhou is a highly experienced engineer with a strong background in CPU and GPU architecture, currently serving as Principal Engineer and Manager at NVIDIA since February 2015. Notable contributions include innovations in CPU RTL design such as the L1 TLB, L2 Cache Universal Request Tracker, and the Return Stack Buffer, as well as formal verification through the Chain Walker framework. Prior to NVIDIA, Liang Zhou worked at AMD as an MTS RTL Design Engineer, focusing on GPU RTL design, and held positions at Juniper Networks and Achronix Semiconductor, gaining expertise in static timing analysis and transistor-level design. Liang Zhou holds a PhD in Electrical Engineering from the University of Arkansas and a Bachelor of Engineering in Telecommunication Engineering from Hubei University.