Larry Ying

Larry Ying is an experienced engineering professional with a strong background in microelectronics and computer systems. Currently serving as Principal Engineer and Lead at Netlist since May 2017, Larry has previously held significant roles including MTS, Design at AMD, and Principal Engineer IC Design at Broadcom. Additional experience includes positions as ASIC Verification Engineer at QLogic, SoftIP Design Engineer at Intel, and Staff Engineer at MaxLinear. Larry began a career in engineering as an ASIC Engineer at Qualcomm and contributed as a Research Assistant at McGill University. Academic credentials include a Master's Degree in Microelectronics and Computer Systems from McGill University.