Valerie Vaz

Valerie Vaz is a skilled Senior ASIC Layout Engineer at Neuranics, with a robust background in analog and mixed-signal design, specializing in advanced processes such as 10nm and 14nm technologies. Prior experience includes roles as Senior Analog Layout Engineer and Analog Layout Engineer at Nanusens, as well as Technical Lead and Senior Layout Engineer I at Sankalp Semiconductor, where responsibilities encompassed leading layout projects and engineering tasks. Valerie's early career included a brief tenure as a Mask Design Engineer trainee at Citrix and an internship focused on Java Basics at Kallows Engineering India Pvt. Ltd. Valerie holds a Bachelor of Engineering degree in Electrical, Electronics, and Communications Engineering from Don Bosco College of Engineering, completed in 2017.