Jerin Xavier

Jerin Xavier has extensive experience in CPU design engineering, currently serving as a CPU Design Engineer at NUVIA Inc since May 2020. Prior to this role, Jerin worked at Intel Corporation from 2016 to May 2020, focusing on Atom CPU design and implementation. From 2011 to 2016, Jerin was at AMD, contributing to the design and implementation of next-generation AMD Zen (RYZEN) and Jaguar x86 CPU cores, with responsibilities including physical design activities and timing closure for successful tape-outs. Earlier experience includes a research assistant position at Arizona State University, where Jerin designed custom radiation-hardened L1 cache as part of a thesis under Dr. Lawrence T. Clark, and a hardware engineering role at Nokia Siemens Networks, specializing in digital design and verification of WLAN ARM-based baseband IPs.