WL

Wenpei Lin

Principal Engineer, IC Packaging at NUVIA

Wenpei Lin possesses extensive experience in IC packaging, currently serving as Principal Engineer at NUVIA Inc since March 2020, focusing on HPC CPU packaging integration, substrate design, and reliability analysis. Prior to this, Wenpei worked as Senior Staff Engineer at Broadcom Limited, overseeing over 40 packaging projects across mobile and networking sectors, and collaborated closely with chip design teams to optimize package design. Wenpei's earlier roles included research and teaching assistant positions at UC Irvine, focusing on advanced interconnect technologies, as well as research assistantships at UNLV and Taiwan Semiconductor Manufacturing Company, where failure analysis and advanced technology qualification were primary responsibilities. Educational qualifications include a Ph.D. in Materials and Manufacturing Technology from UC Irvine, a Master’s in Materials Science and Engineering from National Chiao Tung University, and a Bachelor’s from National Cheng Kung University.

Location

San Francisco, United States

Links


Org chart

No direct reports

Teams


Offices

This person is not in any offices


NUVIA

Nuvia develops processors intended to create high-performance silicon design for a compute-intensive world.It designs processing chipsets for data center servers, thereby delivering a faster, power-efficient, and secure experience to existing data center processors.


Employees

51-200

Links