Greg Baty

Greg Baty is an experienced Senior Verification Engineer at Microsoft Inc. since March 2016, focusing on running function UVM simulations in post-DFT RTL and debugging simulation failures. Baty has also held roles at Qualcomm and QuickLogic as a DFT professional and ASIC Design Engineer, respectively, contributing to the Sensor Hub ASIC project by architecting and coding Verilog RTL. Prior experience includes consulting for Solarflare Communications, where responsibilities encompassed documentation, design, and verification of complex CPU systems for advanced ASIC technology. Baty holds a Master’s Degree in Computer Architecture and Image Processing from the University of Southern California and multiple degrees from the University of Michigan in Digital Signal Processing and Digital Electronics.