Leo John Thomas

Leo John Thomas has a diverse work experience in the field of engineering and design. Leo currently holds the position of Senior Principal Engineer in ASIC Design at Rambus, a role they have held since August 2023. Prior to this, they worked as a Principal Engineer in ASIC Design at Rambus from February 2021 to July 2023. Leo also worked as a Senior Member of Technical Staff II in CAD/EDA at Rambus from April 2018 to February 2021.

Before joining Rambus, Leo worked at Intel Corporation as a Component Design Engineer, specializing in Memory Compiler Design, Automatic Design, and Design Integration from June 2015 to April 2018. Prior to that, they worked as a Component Design Engineer at Intel from June 2012 to June 2015, focusing on PDK Development, Custom Routing, and Placement Methodologies.

Leo's early career includes roles at Arm as an Engineering Consultant in Design Automation, specifically in Std. Cell Design and Release flows from October 2011 to May 2012. Leo also worked at Wipro Technologies as a Project Engineer in VLSI AMS Design Automation from December 2009 to May 2012. Prior to that, they served as an Engineering Consultant in Design Automation at Renesas Electronics from April 2010 to April 2011.

Leo started their career as a Research Associate in the field of Robotics, Haptics, and Virtual Training at the School of Computing, Amrita Vishwa Vidyapeetham, Amritapuri from March 2009 to December 2009.

Leo John Thomas completed their education at Mahatma Gandhi University, where they obtained a Bachelor of Technology (B.Tech.) degree in Electrical, Electronics, and Communications Engineering from 2004 to 2008. Prior to that, they completed their Higher Secondary education in Physical Sciences (Electronics) at IHRD THSS, Mallappally from 2002 to 2004. In addition to their academic qualifications, Leo John Thomas has obtained various certifications from Cadence Design Systems, including exams in Xcelium Simulator, Spectre Simulator Fundamentals, Virtuoso ADE Explorer and Assembler, Virtuoso Layout for Advanced Nodes, SKILL Development of Parameterized Cells, and Spectre Accelerated Parallel Simulator.