Etienne Laurendeau

Etienne Laurendeau has extensive work experience in the field of digital verification and FPGA design. Etienne currently holds the position of Team Leader Digital Verification at SCALINX from April 2023. Prior to this, they worked as a Tech Lead Digital Verification at SCALINX from November 2020 to March 2023.

Before joining SCALINX, Etienne worked at Nokia as an FPGA/SoC Specialist in Design Integration and UVM Verification. Their role involved being a Technical Leader in a team of 20 people, focusing on design integration floorplanning, STA (SDC), lint/CDC design checks, and other related tasks. Etienne worked at Nokia from August 2018 to November 2020.

Etienne's earlier work experience includes working at A.L.S.E. as a Senior FPGA Designer & Certified Instructor. In this role, they were responsible for various aspects of FPGA project management, from specifications to RTL coding, testbenches, simulations, synthesis, and on-board verifications. Etienne had expertise in tools such as Quartus, Timequest, Lattice (Diamond), Actel Microsemi (Libero), and Xilinx (ISE), and strong knowledge of HDL languages like VHDL, Verilog, and System Verilog. Etienne worked at A.L.S.E. from April 2004 to August 2018.

Overall, Etienne Laurendeau has a diverse range of experience in digital verification, FPGA design, and team leadership.

Etienne Laurendeau attended the Institut national des Sciences appliquées de Rennes from 1998 to 2003. Etienne graduated with a degree in Electronics and Communications Systems, specializing in Electrical, Electronics and Communications Engineering.