Chinmaya Mohapatro

Chinmaya Mohapatro is a seasoned professional in the field of Analog IC Design, currently serving as a Senior Manager at Semtech since November 2022, where management of a design team focusing on high-speed LPO and DSP based PMDs for Datacenter and Wireless applications occurs. Prior experience includes a managerial role at Silanna Semiconductor overseeing a layout team for High Performance UHV Analog power management circuits, and a position as a Senior Engineer at Huawei working on Ultra High Speed SerDes in 7nm FinFet technology. Additionally, Chinmaya held the position of Layout Manager at Sankalp Semiconductor, focusing on chip and module level layout design and project management, and began a professional journey as a Project Intern at Cadence Design Systems. Academic qualifications include an MBA in General Management and Consulting from the Telfer School of Management at the University of Ottawa and a Bachelor's degree in Electrical and Electronics Engineering from the National Institute of Science and Technology.