Sarang Kalra

Sarang Kalra is an experienced engineer currently serving as a Senior Design Verification Engineer at Silicon Labs since July 2021, previously holding the position of IC Design Verification Engineer. Prior experience includes working as a Teaching Assistant at the Indian Institute of Technology, Bombay, from July 2019 to June 2021, where responsibilities involved conducting vivas, quizzes, exams, and evaluating answer scripts for various electronics and VLSI design courses. Sarang has also served as a coordinator for Techfest at IIT Bombay in December 2017. Educational qualifications include a Master of Technology in Solid State Devices from the Indian Institute of Technology, Bombay, as well as degrees in Theoretical Physics (Research Scholar) and Physics (M.Sc.) from the same institution and Sri Venkateswara College at Delhi University.