Wai Loon Ngo

Wai Loon Ngo is a Senior Staff Engineer in Design Verification at SkyeChip, where responsibilities include defining IP level test plans, developing UVM-based verification frameworks, and creating functional coverage for cutting-edge die-to-die interconnect IP. Previously, Wai Loon held multiple roles at Intel Corporation including Manager of FPGA Design Verification & Validation, overseeing high-speed serial interface IPs for 5G, and Staff Engineer for FPGA Pre/Post IP Validation, leading system hardware solution validation. Earlier in career, Wai Loon was a Structural & Physical Design Engineer focusing on VLSI design methodologies. Academic qualifications include a Master's degree in Computer & Microelectronics Systems and a Bachelor's degree in Electrical and Electronics Engineering from Universiti Teknologi Malaysia.