Sandeep Battar

Sandeep Battar is a Physical Design Engineer with extensive experience in module level ASIC Physical Design and full chip static timing analysis for process nodes including 20nm, 28nm, and 45nm, utilizing Cadence and Synopsys tools, currently working at Soctronics since July 2011. Prior experience includes a role as a Design Engineer at Wafer Space in 2017 and a System Administrator at the Department of Posts, India from March 2010 to July 2011. Sandeep Battar holds a Bachelor of Technology (B.Tech.) degree in Electronics and Communication Engineering from Sreenidhi Institute of Science and Technology, completed in 2009.