Stéphane Astié

Stéphane Astié is an experienced professional in semiconductor manufacturing and process improvement, currently serving as Project Manager for Strategic Programs at SOITEC since September 2011. Astié has led yield ramp efforts for both 200mm and 300mm SOI and FDSOI technologies while also focusing on yield improvement impacts on gross margins. Prior to SOITEC, Astié worked at Johnson Controls - Saft as a Failure Analysis Engineer, where responsibilities included laboratory planning and equipment selection. From January 1998 to November 2010, Astié held multiple roles at Freescale Semiconductor, including Device Engineer and Defectivity Engineer, leveraging expertise in automotive product ownership and defect rate control. Earlier experience includes a position as R&D Engineer at Motorola, where Astié contributed to electrothermal simulation and manufacturing process development. Astié holds a PhD in Material Science with a focus on Semiconductor Manufacturing Technology from Université Paul Sabatier Toulouse III.