Bhargav Mutyala

Bhargav Mutyala is an experienced analog design engineer currently serving as a Staff Engineer in Analog Design at Synopsys Inc since December 2023. Prior to this, Bhargav held the position of Lead Analog Design Engineer at Excelmax Technologies from June 2023 to December 2023. Bhargav's extensive background includes roles as a Senior Analog Design Engineer at Cerium Systems and Wipro, as well as an Analog Design Engineer at Soctronics. Bhargav began the professional career as an Analog Design Intern at VEDA IIT in 2017. Academic qualifications include a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Vignan's University, completed in 2017, and intermediate education in Mathematics, Physics, and Chemistry from Narayana Junior College.