Joe Lee

Joe Lee has extensive experience in ASIC design and verification, with a career spanning over three decades. From March 2013 to January 2020, Joe served as a Sr Staff Design and Verification Engineer at Synopsys Inc, leading the technical efforts of a 10G serdes PHY product line. Prior roles include Sr. Staff ASIC Engineer and Staff ASIC Designer at Sigma Designs from February 2008 to March 2013, and Senior ASIC Designer at Gennum Corporation from May 1999 to February 2008, where Joe led a team in the development of multiple generations of VXP video processor chips. Additional experience includes ASIC design work at Xylon Research Inc and early career contributions as an Electronics Engineer at Wong's Electronics (HK) Co, focusing on hardware and BIOS development for laptops.