Sonia Singhal

Sonia Singhal is a Principal Engineer at Synopsys, where responsibilities include Timing Analysis for implementation flows and work with the Galaxy Constraint Analyzer since January 2008. Prior experience includes serving as a Graduate Research Assistant at Carnegie Mellon University from August 2005 to December 2007, focusing on Placement Technologies and Statistical Static Timing Analysis. Earlier roles include MTS at Cadence Design Systems, emphasizing Physical Optimization from May 2004 to July 2005, and Software Engineer at STMicroelectronics, specializing in FPGA RTL Synthesis from August 2001 to April 2004. Sonia Singhal holds a Master of Science in Electrical and Computer Engineering from Carnegie Mellon University and a Bachelor of Engineering in Instrumentation and Control from Delhi University.