Nagendra Dwarakanath

Nagendra Dwarakanath is a seasoned professional with extensive experience in system architecture and software development, currently serving as a System Architect - SMTS at Texas Instruments since December 1998. In this role, Nagendra focuses on SOC and IP specification development methodologies to enhance software correctness and efficiency while streamlining design workflows for improved product quality. Previously, as an Automotive Software Architect, Nagendra led the architecture for a multi-core SOC and optimized software pipelines for safety-critical applications. Nagendra has also held managerial and engineering positions, overseeing simulation teams and developing tools for pre-silicon architecture. Prior experience includes working as a Developer at Motorola India Electronics Ltd. Nagendra holds a PhD in Computer Architecture and a Master's degree in System Science and Automation from the Indian Institute of Science, as well as a BE in Computer Science from Bangalore University.