Arteris
Santhosh Injineri has a diverse work experience spanning various roles and companies. Santhosh is currently working at Arteris IP as a Senior Application Engineer, a position they have held since March 2022. Prior to this role, they served as a Network-on-Chip Solutions Architect at the same company. Santhosh also has experience as a Field Application Engineer at Arteris IP, a position they held starting in January 2019.
Before joining Arteris IP, Santhosh worked at Qualcomm as a Sr. Lead Engineer in the System Performance team from April 2016 to January 2019. Their responsibilities included ensuring the design meets performance requirements, bringing up SOCs on emulation, and driving improvements in the test bench collateral.
Santhosh also has experience working at Cadence Design Systems, where they held multiple roles. Santhosh was a Lead Application Engineer from an unspecified date in 2015 to March 2016 and a Senior Sales Application Engineer from April 2013 to March 2016. In these roles, they worked on bringing up designs and driving testing flows on emulation platforms.
Additionally, Santhosh worked as an Intern at Cadence Design Systems, where they were involved in TLM modeling for memory controllers. Santhosh also served as a Master Thesis student, working on system-level modeling and verification.
Earlier in their career, Santhosh gained experience at Techn. University of Kaiserslautern / TU as a Master Student and Research Assistant. During this time, they worked on analyzing power consumption of CPUs and designed tools for Fault Tree Analysis.
Santhosh also worked at Sun Microsystems as a Member of Technical Staff, where they developed a test framework using shell scripting and conducted test coverage analysis. Before that, they were a Software Engineer at Hewlett-Packard, where they performed manual and automated testing and worked on porting applications onto HP-UX.
Santhosh started their career as an Associate Software Engineer at CodeTheatre, where they worked on projects related to 3DES encryption. Overall, Santhosh has a wide range of experience in application engineering, performance analysis, emulation, testing, and verification.
Santhosh Injineri pursued their Bachelor of Engineering (BE) degree in Electronics and Communication Engineering from Visvesvaraya Technological University. Santhosh attended the university from 2001 to 2005. Later, they pursued a Master of Science (MS) degree in Embedded Computing from RPTU Kaiserslautern-Landau. Santhosh attended the university from 2010 to 2012.
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Arteris
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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.