Digital Design Manager

Job Description 

We are looking for a Digital Design Manager with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers' connectivity solutions. The candidate must have a good knowledge of communication and interface standards, base protocols such as PCI-Express (Gen-3 and above), Ethernet, NVMe, DDR, etc. 

Basic qualifications: 

• Strong academic and technical background in Electrical or Computer Engineering. A bachelor is EE is required and a Master's degree is preferred. 

• 12+ years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. 

• 3+ years’ experience in technical leadership or management experience.  

• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare in advance for customer meetings, and work mostly independently with minimal guidance and supervision. 

• Entrepreneurial, open-minded behavior and must have a can-do attitude. Think and act fast with always the customer in mind! 

• Authorized to work in the US and start immediately. 

Required experience: 

• Hands-on, thorough knowledge of at least one high-speed protocol such as PEIe, CXL, Ethernet, NVMe, DDR etc. 

• Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, and DFT, etc. 

• Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production.     Extensive collaboration with software development teams is needed.  

• Experience using Cadence and/or Synopsys digital design tools/flows.  

• Knowledge in design for test (DFT), stuck at and transition scan test insertion. 

• Familiarity with UVM based design verification 

• Silicon bring-up and debug expertise 

• Small-geometry CMOS (≤ 28nm, 16nm) design 

Preferred experience: 

• Scripting with Python or other equivalent programming languages. 

• Development / support for PCIE and DDR based products. PCIe or Ethernet Switch products. Familiarity with security standards 

• Strong methodology mindset with a track record of developing ASIC development methodologies. 

The base salary range is $184,000 USD – $2,600,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.