Auradine
Dharmendra Patel is currently serving as a Sr. Principal Engineer in ASIC Verification at Auradine since May 2023. Before this role, Dharmendra worked as a Sr. Manager in ASIC Verification at Palo Alto Networks from August 2012 to May 2023. Prior to that, Dharmendra held various engineering roles at companies like Altera, Aquantia, and einfochips. Dharmendra also has experience as a lecturer at NIRMA University. Dharmendra's expertise lies in building ASICs, ARM based SoC verification, and Ethernet PHY chip verification using different methodologies.