IC Enable
Paul Graves is a seasoned engineering professional with extensive experience in the semiconductor industry. Currently serving as a Layout Design Engineer at IC Enable since April 2013, Paul specializes in deep sub-micron and multi-pattern design. Prior roles include Lead Design Engineer and Layout Designer at Intersil, where responsibilities encompassed analog IC design, physical design of various interfaces, and supervision of tape-out processes. Earlier positions at Harris Corporation involved component engineering and product engineering for military and aerospace applications, while initial roles at RCA Solid State and GE provided foundational expertise in product and process engineering. Paul holds a Bachelor of Science in Electrical Engineering (BSEE) from the University of Wisconsin-Madison.
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IC Enable
IC Enable has a success delivering design and layout services to demanding Fortune 50 customers since 2004. Our team has experience with full-custom chip layout, seamlessly taking our customers from planning, to top-level PG hand-off. We have extensive experience with analog circuit layout techniques related to critical matching, shielding, sensitive routes, high voltage, RF requirements, and routing considerations. The IC Enable model allows us to supply clients with the needed additional capacity and expertise for layout and design projects. With the ability to staff both off-site and on-site, IC Enable can deliver projects quickly and efficiently to meet client needs. Now is an exciting time to join our team as we continue to change the industry through experience in technology development, full-custom ASIC and electronics development across the Semiconductor, Medical and Defense industries, including some of the most challenging fabrication processes and product applications. We are continually looking to expand our team of experienced and new engineers. Come join our team!