Aishwarya Mahesh

Aishwarya Mahesh is a Senior Staff Design Verification Engineer at Marvell Technology since January 2022, previously serving as a Staff Design Verification Engineer. Prior experience includes a role as a Pre-Si Functional Simulation Engineer at Intel Corporation from January 2018 to October 2019, where responsibilities encompassed developing pre-silicon Virtual Platform QA test plans and validating NVMe Controller models, alongside identifying critical bugs. Aishwarya also interned with the Intel Architecture Core Group, focusing on logical changes for the pre-fetcher block in mid-level cache. Aishwarya holds a Master of Science in Electrical Engineering with a specialization in VLSI from San Jose State University (2020-2021) and a Bachelor's degree from RV College of Engineering (2014-2018).