Ziyuan Ning

Ziyuan Ning is an accomplished engineer specializing in analog IC design and RF/MS IC design. Currently serving as a Senior Staff Engineer at Marvell Technology since December 2022, Ziyuan is involved in the development of 2.5/5/10G BASE-T full-duplex transceivers. Prior to this role, Ziyuan held the position of Senior RF/MS IC Design Engineer at MaxLinear from October 2019 to November 2022, contributing to the Mxl Keystone 800G PAM4 DSP A0/B0 project and undertaking internships focused on the research phase of 100G Serdes clocking. Ziyuan obtained a Master of Science in Electrical and Computer Engineering from UC San Diego in 2019 and a Bachelor of Science in Physics from Shandong University in 2018.