Xinyi Jiang

Xinyi Jiang is a Senior Analog Design Engineer at Monolithic Power Systems, Inc. since January 2024, previously serving as an Analog Design Engineer at Intel Corporation from July 2019 to January 2024. At Intel, Xinyi contributed to significant projects including the IFS project focused on SAR ADC design and validation, UCIe project involving high-speed receivers, and 3DXP project on various analog components. Earlier roles include a Research Assistant at the University of California, Berkeley, where Xinyi designed a local oscillator for Bluetooth protocol, and at Purdue University, where Xinyi worked on Human Body Communication in the SPARC Lab and published two academic papers. Xinyi holds a Master's degree in Electrical and Electronics Engineering from the University of California, Berkeley, and a Bachelor's degree from Purdue University.