Arun G

Arun G is a Senior Analog Design Engineer at Renesas Electronics since August 2023, specializing in DDR Buffer chip design. Prior to this role, Arun worked as an Analog Circuit Designer at Intel Corporation from September 2021 to August 2023, focusing on viewpin blocks including a Strongarm latch circuit capable of operating up to 4Gbps. From May 2017 to September 2021, Arun was employed at Rambus as an Analog Circuit Designer, with expertise in DDR5 RCD buffer chip design and successful silicon bring-up of regulators and bandgap reference (BGR) circuits. Arun's educational background includes a Master of Technology in Microelectronics from Manipal Institute of Technology (2016-2018), a Bachelor of Technology in Electronics and Communications Engineering from the Institute of Engineering and Technology, Calicut (2011-2014), and a Diploma in Electronics Engineering from GPTC Thrikkaripur (2009-2011).