Jaimil Patel

Jaimil Patel is a seasoned Sr. Verification Engineer at Renesas Electronics, with experience in writing and integrating UVM Agent codes for clock glitch injection and SCAN CHAIN testing since July 2021. Prior to this role, Jaimil worked as a Design Engineering Intern at Mixel, Inc., where responsibilities included designing RTL synchronizer modules and generating bit files for FPGA. Jaimil's career began as a Hardware and Software Engineer at Quixote India, contributing to the development of a Car Telematics Device by programming using Python, C, and Verilog, and leading a team to implement a Dead Reckoning algorithm. Jaimil holds a Graduate degree in Electrical and Electronics Engineering from San José State University, a Pre-Master's degree in Integrated Circuit Design from the University of Twente, and a Bachelor's degree in Instrumentation and Controls from L.J. Institute Of Engg And Tech.