Vivek Jayanand

Vivek Jayanand possesses extensive experience in the semiconductor industry, currently serving as MTS in SerDes Electrical Bring-Up and Characterization at Rivos Inc. since June 2025. Prior to this role, Vivek worked as a SERDES Validation Engineer at Achronix Semiconductor Corporation from September 2022 to May 2025. Vivek's tenure at Western Digital spanned eight years, where positions included Senior Manager of SERDES Validation, Technologist, and Principal Engineer of the Host Interface Team. Earlier career experience includes roles as Staff Field Applications Engineer and Senior Hardware Engineer at Marvell Semiconductor, Advanced Applications Engineer at Altera, and Product Engineer at Integrated Device Technology Inc. Vivek holds a Master of Science (M.S.) degree in Electrical Engineering from the University of Southern California.