Sven Rheindt

Sven Rheindt is a Project Leader at Rohde & Schwarz, overseeing ASIC Development and Digital Backend Oscilloscope projects since November 2021, while also serving as a Development Engineer in Digital ASIC Design. Prior to this role, Sven was a Research Associate at the Technical University of Munich (TUM) from January 2016 to October 2021, focusing on doctoral research in Integrated Systems. Early experience includes a Masterarbeit and a Bachelor's thesis at ARRI, where projects involved FPGA development and dynamic partial reconfiguration. Sven holds a Master of Science in Electrical Engineering and Information Technology from TUM and a Bachelor of Science in the same field from TUM as well. Additionally, Sven participated in academic studies at the Georgia Institute of Technology in 2014.