Prigish George Abraham

Prigish George Abraham is an experienced Senior FPGA RTL Design Engineer currently at VVDN Technologies since July 2018, also previously serving as an FPGA RTL Design Engineer. Before this role, Prigish worked at Valtix as a Design Verification Engineer from September 2018 to January 2020 and began as a Graduate Engineering Trainee at Funfirst Globalskillers Pvt. Ltd. in March 2016. Educational qualifications include a Master of Technology (MTech) in Advanced Electronics and Communication from Rajiv Gandhi Institute of Technology, Kottayam, completed in 2018, and a Bachelor of Technology (B.Tech.) in Electronics and Communications Engineering from the College of Engineering, Chengannoor, earned in 2015.